In a semiconductor memory device, memory cells may be susceptible to errors based on a transient error or a soft error. The errors may be due to a transient error caused by noises from surrounding components in the device with high-density. Soft errors may be caused by background radiation. Memories have been developed that include error detection and/or error correcting codes (ECC) to correct these errors.
A compression circuit in the semiconductor memory device may execute a test mode referred to as a “compression mode” for dynamic random access memory (DRAM), in order to detect and correct errors. In the compression mode, for example, data of 128 bits may be divided into sixteen sets of 8-bit data and each set of 8-bit data is compared with an internal register value (eight bits). FIG. 1A is an example of a semiconductor memory device with the compression mode. FIG. 1B is a schematic diagram of a compression circuit in FIG. 1A. In a write operation, 128 bits may be written by setting sixteen sets of 8-bit data to a memory cell array. In a read operation, read data of sixteen sets are compared with data in a register on the 8-bit unit basis so that the matched results are collectively outputted by an OR circuit. That is, if there merely is a 1-bit mismatch in the read data, the mismatch may still be detected as an error and the detected one bit error leads to a fail result of the read data in this configuration.
FIG. 2 is a schematic diagram of a DRAM chip and a controller chip. As shown in FIG. 2, a controller chip, such as a system-on-chip (SoC), may also include a built-in ECC circuit and syndromes and data are exchanged between the DRAM chip and the SoC. In this system configuration, the system is able to execute data processing regardless of some defective portions of data (e.g. data including single bit errors). For example, the DRAM chip that has an error(s) may be nonetheless usable in the system if the SoC has correction capability for the error. Thus, a test mode which ignores some errors may maximize a yield on a wafer and may be desired.